git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From 691deae097b2583a4e9890307c684ce9f58aca78 Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Tue, 24 May 2016 15:03:33 +0530
   4 Subject: [PATCH 45/93] board/freescale/ls1012afrdm: Add support of Ethernet
   5
   6 Add support of SGMII Ethernet present on FRDM board.
   7 Also add support of PHY reset.
   8
   9 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  10 ---
  11  board/freescale/ls1012afrdm/Makefile      |    1 +
  12  board/freescale/ls1012afrdm/eth.c         |   86 +++++++++++++++++++++++++++++
  13  board/freescale/ls1012afrdm/ls1012afrdm.c |    5 --
  14  include/configs/ls1012afrdm.h             |    5 ++
  15  4 files changed, 92 insertions(+), 5 deletions(-)
  16  create mode 100644 board/freescale/ls1012afrdm/eth.c
  17
  18 diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
  19 index dbfa2ce..1364f22 100644
  20 --- a/board/freescale/ls1012afrdm/Makefile
  21 +++ b/board/freescale/ls1012afrdm/Makefile
  22 @@ -5,3 +5,4 @@
  23  #
  24
  25  obj-y += ls1012afrdm.o
  26 +obj-y += eth.o
  27 diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
  28 new file mode 100644
  29 index 0000000..8ae3f45
  30 --- /dev/null
  31 +++ b/board/freescale/ls1012afrdm/eth.c
  32 @@ -0,0 +1,86 @@
  33 +/*
  34 + * Copyright 2016 Freescale Semiconductor, Inc.
  35 + *
  36 + * SPDX-License-Identifier:    GPL-2.0+
  37 + */
  38 +
  39 +#include <common.h>
  40 +#include <asm/io.h>
  41 +#include <netdev.h>
  42 +#include <fm_eth.h>
  43 +#include <fsl_mdio.h>
  44 +#include <malloc.h>
  45 +#include <fsl_dtsec.h>
  46 +#include <asm/arch/soc.h>
  47 +#include <asm/arch-fsl-layerscape/config.h>
  48 +#include <asm/arch/fsl_serdes.h>
  49 +
  50 +#include "../../../drivers/net/pfe_eth/pfe_eth.h"
  51 +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
  52 +
  53 +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  54 +
  55 +#define MASK_ETH_PHY_RST       0x00000100
  56 +
  57 +void reset_phy(void)
  58 +{
  59 +       unsigned int val;
  60 +       ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_GPIO1_ADDR);
  61 +
  62 +       setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
  63 +
  64 +       val = in_be32(&pgpio->gpdat);
  65 +       setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
  66 +       mdelay(10);
  67 +
  68 +       val = in_be32(&pgpio->gpdat);
  69 +       setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
  70 +       mdelay(50);
  71 +}
  72 +
  73 +int board_eth_init(bd_t *bis)
  74 +{
  75 +#ifdef CONFIG_FSL_PPFE
  76 +        struct mii_dev *bus;
  77 +       struct mdio_info mac1_mdio_info;
  78 +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  79 +
  80 +
  81 +       /*TODO Following config should be done for all boards, where is the right place to put this */
  82 +       out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
  83 +       out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
  84 +
  85 +       /*CCI-400 QoS settings for PFE */
  86 +       out_be32(&scfg->wr_qos1, 0x0ff00000);
  87 +       out_be32(&scfg->rd_qos1, 0x0ff00000);
  88 +
  89 +       /* Set RGMII into 1G + Full duplex mode */
  90 +       out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
  91 +
  92 +
  93 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
  94 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
  95 +
  96 +       mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
  97 +       mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  98 +
  99 +       bus = ls1012a_mdio_init(&mac1_mdio_info);
 100 +       if(!bus)
 101 +       {
 102 +               printf("Failed to register mdio \n");
 103 +               return -1;
 104 +       }
 105 +
 106 +       /*MAC1 */
 107 +       ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 108 +       ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
 109 +
 110 +       /*MAC2 */
 111 +       ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 112 +       ls1012a_set_phy_address_mode(1,  EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
 113 +
 114 +
 115 +       cpu_eth_init(bis);
 116 +#endif
 117 +       return pci_eth_init(bis);
 118 +}
 119 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
 120 index 6be8951..6856250 100644
 121 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c
 122 +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
 123 @@ -133,11 +133,6 @@ int dram_init(void)
 124         return 0;
 125  }
 126
 127 -int board_eth_init(bd_t *bis)
 128 -{
 129 -       return pci_eth_init(bis);
 130 -}
 131 -
 132  int board_early_init_f(void)
 133  {
 134         fsl_lsch2_early_init_f();
 135 diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
 136 index 3231ab7..5e619c1 100644
 137 --- a/include/configs/ls1012afrdm.h
 138 +++ b/include/configs/ls1012afrdm.h
 139 @@ -18,8 +18,13 @@
 140  #define CONFIG_SYS_MEMTEST_START       0x80000000
 141  #define CONFIG_SYS_MEMTEST_END         0x9fffffff
 142
 143 +#ifdef CONFIG_FSL_PPFE
 144 +#define EMAC1_PHY_ADDR          0x2
 145 +#define EMAC2_PHY_ADDR          0x1
 146  #define CONFIG_PHYLIB
 147  #define CONFIG_PHY_REALTEK
 148 +#define CONFIG_RESET_PHY_R
 149 +#endif
 150  /*
 151  * USB
 152  */
 153 --
 154 1.7.9.5
 155