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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH 1/2] net: phy: cherry-pick Broadcom drivers updates from
3 v4.10-rc1
4
5 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
6 ---
7
8 --- a/drivers/net/phy/broadcom.c
9 +++ b/drivers/net/phy/broadcom.c
10 @@ -18,7 +18,7 @@
11 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/brcmphy.h>
14 -
15 +#include <linux/of.h>
16
17 #define BRCM_PHY_MODEL(phydev) \
18 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
19 @@ -30,11 +30,49 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
20 MODULE_AUTHOR("Maciej W. Rozycki");
21 MODULE_LICENSE("GPL");
22
23 +static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
24 +{
25 + /* The register must be written to both the Shadow Register Select and
26 + * the Shadow Read Register Selector
27 + */
28 + phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
29 + regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
30 + return phy_read(phydev, MII_BCM54XX_AUX_CTL);
31 +}
32 +
33 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
34 {
35 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
36 }
37
38 +static int bcm54810_config(struct phy_device *phydev)
39 +{
40 + int rc, val;
41 +
42 + val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
43 + val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
44 + rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
45 + val);
46 + if (rc < 0)
47 + return rc;
48 +
49 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
50 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
51 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
52 + rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
53 + val);
54 + if (rc < 0)
55 + return rc;
56 +
57 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
58 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
59 + rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
60 + if (rc < 0)
61 + return rc;
62 +
63 + return 0;
64 +}
65 +
66 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
67 static int bcm50610_a0_workaround(struct phy_device *phydev)
68 {
69 @@ -207,6 +245,12 @@ static int bcm54xx_config_init(struct ph
70 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
71 bcm54xx_adjust_rxrefclk(phydev);
72
73 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
74 + err = bcm54810_config(phydev);
75 + if (err)
76 + return err;
77 + }
78 +
79 bcm54xx_phydsp_config(phydev);
80
81 return 0;
82 @@ -304,6 +348,7 @@ static int bcm5482_read_status(struct ph
83
84 static int bcm5481_config_aneg(struct phy_device *phydev)
85 {
86 + struct device_node *np = phydev->dev.of_node;
87 int ret;
88
89 /* Aneg firsly. */
90 @@ -334,6 +379,49 @@ static int bcm5481_config_aneg(struct ph
91 phy_write(phydev, 0x18, reg);
92 }
93
94 + if (of_property_read_bool(np, "enet-phy-lane-swap")) {
95 + /* Lane Swap - Undocumented register...magic! */
96 + ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
97 + 0x11B);
98 + if (ret < 0)
99 + return ret;
100 + }
101 +
102 + return ret;
103 +}
104 +
105 +static int bcm54612e_config_aneg(struct phy_device *phydev)
106 +{
107 + int ret;
108 +
109 + /* First, auto-negotiate. */
110 + ret = genphy_config_aneg(phydev);
111 +
112 + /* Clear TX internal delay unless requested. */
113 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
114 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
115 + /* Disable TXD to GTXCLK clock delay (default set) */
116 + /* Bit 9 is the only field in shadow register 00011 */
117 + bcm_phy_write_shadow(phydev, 0x03, 0);
118 + }
119 +
120 + /* Clear RX internal delay unless requested. */
121 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
122 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
123 + u16 reg;
124 +
125 + /* Errata: reads require filling in the write selector field */
126 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
127 + MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
128 + reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
129 + /* Disable RXD to RXC delay (default set) */
130 + reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
131 + /* Clear shadow selector field */
132 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
133 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
134 + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
135 + }
136 +
137 return ret;
138 }
139
140 @@ -488,6 +576,19 @@ static struct phy_driver broadcom_driver
141 .config_intr = bcm_phy_config_intr,
142 .driver = { .owner = THIS_MODULE },
143 }, {
144 + .phy_id = PHY_ID_BCM54612E,
145 + .phy_id_mask = 0xfffffff0,
146 + .name = "Broadcom BCM54612E",
147 + .features = PHY_GBIT_FEATURES |
148 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
149 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
150 + .config_init = bcm54xx_config_init,
151 + .config_aneg = bcm54612e_config_aneg,
152 + .read_status = genphy_read_status,
153 + .ack_interrupt = bcm_phy_ack_intr,
154 + .config_intr = bcm_phy_config_intr,
155 + .driver = { .owner = THIS_MODULE },
156 +}, {
157 .phy_id = PHY_ID_BCM54616S,
158 .phy_id_mask = 0xfffffff0,
159 .name = "Broadcom BCM54616S",
160 @@ -527,6 +628,19 @@ static struct phy_driver broadcom_driver
161 .config_intr = bcm_phy_config_intr,
162 .driver = { .owner = THIS_MODULE },
163 }, {
164 + .phy_id = PHY_ID_BCM54810,
165 + .phy_id_mask = 0xfffffff0,
166 + .name = "Broadcom BCM54810",
167 + .features = PHY_GBIT_FEATURES |
168 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
169 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
170 + .config_init = bcm54xx_config_init,
171 + .config_aneg = bcm5481_config_aneg,
172 + .read_status = genphy_read_status,
173 + .ack_interrupt = bcm_phy_ack_intr,
174 + .config_intr = bcm_phy_config_intr,
175 + .driver = { .owner = THIS_MODULE },
176 +}, {
177 .phy_id = PHY_ID_BCM5482,
178 .phy_id_mask = 0xfffffff0,
179 .name = "Broadcom BCM5482",
180 @@ -612,9 +726,11 @@ static struct mdio_device_id __maybe_unu
181 { PHY_ID_BCM5411, 0xfffffff0 },
182 { PHY_ID_BCM5421, 0xfffffff0 },
183 { PHY_ID_BCM5461, 0xfffffff0 },
184 + { PHY_ID_BCM54612E, 0xfffffff0 },
185 { PHY_ID_BCM54616S, 0xfffffff0 },
186 { PHY_ID_BCM5464, 0xfffffff0 },
187 { PHY_ID_BCM5481, 0xfffffff0 },
188 + { PHY_ID_BCM54810, 0xfffffff0 },
189 { PHY_ID_BCM5482, 0xfffffff0 },
190 { PHY_ID_BCM50610, 0xfffffff0 },
191 { PHY_ID_BCM50610M, 0xfffffff0 },
192 --- a/include/linux/brcmphy.h
193 +++ b/include/linux/brcmphy.h
194 @@ -13,11 +13,13 @@
195 #define PHY_ID_BCM5241 0x0143bc30
196 #define PHY_ID_BCMAC131 0x0143bc70
197 #define PHY_ID_BCM5481 0x0143bca0
198 +#define PHY_ID_BCM54810 0x03625d00
199 #define PHY_ID_BCM5482 0x0143bcb0
200 #define PHY_ID_BCM5411 0x00206070
201 #define PHY_ID_BCM5421 0x002060e0
202 #define PHY_ID_BCM5464 0x002060b0
203 #define PHY_ID_BCM5461 0x002060c0
204 +#define PHY_ID_BCM54612E 0x03625e60
205 #define PHY_ID_BCM54616S 0x03625d10
206 #define PHY_ID_BCM57780 0x03625d90
207
208 @@ -52,6 +54,7 @@
209 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
210 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
211 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
212 +
213 /* Broadcom BCM7xxx specific workarounds */
214 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
215 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
216 @@ -102,11 +105,14 @@
217 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
218
219 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
220 +#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
221 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
222 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
223 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
224 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
225 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
226
227 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
228 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
229
230 /*
231 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
232 @@ -186,6 +192,12 @@
233 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
234 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
235
236 +/* BCM54810 Registers */
237 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
238 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
239 +#define BCM54810_SHD_CLK_CTL 0x3
240 +#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
241 +
242
243 /*****************************************************************************/
244 /* Fast Ethernet Transceiver definitions. */
245 --- a/drivers/net/phy/Kconfig
246 +++ b/drivers/net/phy/Kconfig
247 @@ -77,7 +77,7 @@ config BROADCOM_PHY
248 select BCM_NET_PHYLIB
249 ---help---
250 Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
251 - BCM5481 and BCM5482 PHYs.
252 + BCM5481, BCM54810 and BCM5482 PHYs.
253
254 config BCM_CYGNUS_PHY
255 tristate "Drivers for Broadcom Cygnus SoC internal PHY"
Staging tree of Piotr Dymacz