git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 21a2802a8365cfa82cc02187c1f95136d85592ad Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Fri, 8 Dec 2023 15:51:59 +0100
   4 Subject: [PATCH 12/13] net: phy: at803x: move at8035 specific DT parse to
   5  dedicated probe
   6
   7 Move at8035 specific DT parse for clock out frequency to dedicated probe
   8 to make at803x probe function more generic.
   9
  10 This is to tidy code and no behaviour change are intended.
  11
  12 Detection logic is changed, we check if the clk 25m mask is set and if
  13 it's not zero, we assume the qca,clk-out-frequency property is set.
  14
  15 The property is checked in the generic at803x_parse_dt called by
  16 at803x_probe.
  17
  18 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  19 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  20 Signed-off-by: David S. Miller <davem@davemloft.net>
  21 ---
  22  drivers/net/phy/at803x.c | 60 +++++++++++++++++++++++++++-------------
  23  1 file changed, 41 insertions(+), 19 deletions(-)
  24
  25 --- a/drivers/net/phy/at803x.c
  26 +++ b/drivers/net/phy/at803x.c
  27 @@ -638,23 +638,6 @@ static int at803x_parse_dt(struct phy_de
  28
  29                 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
  30                 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
  31 -
  32 -               /* Fixup for the AR8030/AR8035. This chip has another mask and
  33 -                * doesn't support the DSP reference. Eg. the lowest bit of the
  34 -                * mask. The upper two bits select the same frequencies. Mask
  35 -                * the lowest bit here.
  36 -                *
  37 -                * Warning:
  38 -                *   There was no datasheet for the AR8030 available so this is
  39 -                *   just a guess. But the AR8035 is listed as pin compatible
  40 -                *   to the AR8030 so there might be a good chance it works on
  41 -                *   the AR8030 too.
  42 -                */
  43 -               if (phydev->drv->phy_id == ATH8030_PHY_ID ||
  44 -                   phydev->drv->phy_id == ATH8035_PHY_ID) {
  45 -                       priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
  46 -                       priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
  47 -               }
  48         }
  49
  50         ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
  51 @@ -1635,6 +1618,45 @@ static int at8031_config_intr(struct phy
  52         return at803x_config_intr(phydev);
  53  }
  54
  55 +static int at8035_parse_dt(struct phy_device *phydev)
  56 +{
  57 +       struct at803x_priv *priv = phydev->priv;
  58 +
  59 +       /* Mask is set by the generic at803x_parse_dt
  60 +        * if property is set. Assume property is set
  61 +        * with the mask not zero.
  62 +        */
  63 +       if (priv->clk_25m_mask) {
  64 +               /* Fixup for the AR8030/AR8035. This chip has another mask and
  65 +                * doesn't support the DSP reference. Eg. the lowest bit of the
  66 +                * mask. The upper two bits select the same frequencies. Mask
  67 +                * the lowest bit here.
  68 +                *
  69 +                * Warning:
  70 +                *   There was no datasheet for the AR8030 available so this is
  71 +                *   just a guess. But the AR8035 is listed as pin compatible
  72 +                *   to the AR8030 so there might be a good chance it works on
  73 +                *   the AR8030 too.
  74 +                */
  75 +               priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
  76 +               priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
  77 +       }
  78 +
  79 +       return 0;
  80 +}
  81 +
  82 +/* AR8030 and AR8035 shared the same special mask for clk_25m */
  83 +static int at8035_probe(struct phy_device *phydev)
  84 +{
  85 +       int ret;
  86 +
  87 +       ret = at803x_probe(phydev);
  88 +       if (ret)
  89 +               return ret;
  90 +
  91 +       return at8035_parse_dt(phydev);
  92 +}
  93 +
  94  static int qca83xx_config_init(struct phy_device *phydev)
  95  {
  96         u8 switch_revision;
  97 @@ -2107,7 +2129,7 @@ static struct phy_driver at803x_driver[]
  98         PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
  99         .name                   = "Qualcomm Atheros AR8035",
 100         .flags                  = PHY_POLL_CABLE_TEST,
 101 -       .probe                  = at803x_probe,
 102 +       .probe                  = at8035_probe,
 103         .config_aneg            = at803x_config_aneg,
 104         .config_init            = at803x_config_init,
 105         .soft_reset             = genphy_soft_reset,
 106 @@ -2128,7 +2150,7 @@ static struct phy_driver at803x_driver[]
 107         .phy_id                 = ATH8030_PHY_ID,
 108         .name                   = "Qualcomm Atheros AR8030",
 109         .phy_id_mask            = AT8030_PHY_ID_MASK,
 110 -       .probe                  = at803x_probe,
 111 +       .probe                  = at8035_probe,
 112         .config_init            = at803x_config_init,
 113         .link_change_notify     = at803x_link_change_notify,
 114         .set_wol                = at803x_set_wol,