git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 82b892c3df4893b123681b2ba725c0861e0112a4 Mon Sep 17 00:00:00 2001
   2 From: Robin Gong <yibin.gong@nxp.com>
   3 Date: Tue, 13 Mar 2018 02:03:09 +0800
   4 Subject: [PATCH] MLK-17782 dma: fsl-edma-v3: fix issue reported by Coverity
   5
   6 Fix below issue reported by Coverity, actually, don't need this
   7 condition check here, remove it.
   8
   9 CID undefined (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)operator_confusion:
  10 (16UL /* 1UL << 4 */) | (__u16)(__le16)tcd->csr is always 1/true regardless of the values of its operand.
  11 This occurs as the logical first operand of "&&".
  12
  13 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  14 Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
  15 (cherry picked from commit ab942110975cadcde57ab1110df03f526bd3fec5)
  16 ---
  17  drivers/dma/fsl-edma-v3.c | 6 ++----
  18  1 file changed, 2 insertions(+), 4 deletions(-)
  19
  20 --- a/drivers/dma/fsl-edma-v3.c
  21 +++ b/drivers/dma/fsl-edma-v3.c
  22 @@ -1,7 +1,7 @@
  23  /*
  24   * drivers/dma/fsl-edma3-v3.c
  25   *
  26 - * Copyright 2017 NXP .
  27 + * Copyright 2017-2018 NXP .
  28   *
  29   * Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c
  30   * but changed to meet the IP change on i.MX8QM: every dma channel is specific
  31 @@ -451,9 +451,7 @@ static void fsl_edma3_set_tcd_regs(struc
  32         writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
  33
  34         /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */
  35 -       if ((EDMA_TCD_CSR_E_SG | le16_to_cpu(tcd->csr)) &&
  36 -               EDMA_CH_CSR_DONE | readl(addr + EDMA_CH_CSR))
  37 -               writel(EDMA_CH_CSR_DONE, addr + EDMA_CH_CSR);
  38 +       writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR);
  39
  40         writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
  41  }