git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 136762e82a9c4974c15b0525245092d11a825cee Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Wed, 12 Jul 2017 18:00:58 +0800
   4 Subject: [PATCH] MLK-15960-2: ASoC: fsl_sai: refine the pm runtime function
   5
   6 In imx8qm/imx8qxp, the power domain of IP is enabled when
   7 pm_runtime_get_sync() is called, and disabled when pm_runtime
   8 _put_sync() is called. when power domain is disabled, the value
   9 of registers will lost, so we need to use the regcache_sync()
  10 to restore the registers in fsl_sai_runtime_resume.
  11
  12 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  13 ---
  14  sound/soc/fsl/fsl_sai.c | 4 ++++
  15  1 file changed, 4 insertions(+)
  16
  17 --- a/sound/soc/fsl/fsl_sai.c
  18 +++ b/sound/soc/fsl/fsl_sai.c
  19 @@ -1097,6 +1097,8 @@ static int fsl_sai_probe(struct platform
  20
  21         pm_runtime_enable(&pdev->dev);
  22
  23 +       regcache_cache_only(sai->regmap, true);
  24 +
  25         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
  26                                               &sai->cpu_dai_drv, 1);
  27         if (ret)
  28 @@ -1140,6 +1142,8 @@ static int fsl_sai_runtime_suspend(struc
  29  {
  30         struct fsl_sai *sai = dev_get_drvdata(dev);
  31
  32 +       regcache_cache_only(sai->regmap, true);
  33 +
  34         if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
  35                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
  36