git.openwrt.org Git - openwrt/staging/hauke.git/blob

   1 From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001
   2 From: Sham Muthayyan <smuthayy@codeaurora.org>
   3 Date: Mon, 15 Jun 2020 23:06:07 +0200
   4 Subject: PCI: qcom: Support pci speed set for ipq806x
   5
   6 Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to
   7 some hardware limitations. Add support for speed setting defined by the
   8 max-link-speed binding. If not defined the max speed is set to GEN2 by
   9 default.
  10
  11 Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com
  12 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  13 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  14 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  15 Reviewed-by: Rob Herring <robh@kernel.org>
  16 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  17 ---
  18
  19 Backported with light changes:
  20 * One include is missing in kernel 5.4
  21
  22  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
  23  1 file changed, 13 insertions(+)
  24
  25 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  26 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  27 @@ -27,6 +27,7 @@
  28  #include <linux/slab.h>
  29  #include <linux/types.h>
  30
  31 +#include "../../pci.h"
  32  #include "pcie-designware.h"
  33
  34  #define PCIE20_PARF_SYS_CTRL                   0x00
  35 @@ -98,6 +99,8 @@
  36  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE     0x358
  37  #define SLV_ADDR_SPACE_SZ                      0x10000000
  38
  39 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2       0xa0
  40 +
  41  #define QCOM_PCIE_2_1_0_MAX_SUPPLY     3
  42  #define QCOM_PCIE_2_1_0_MAX_CLOCKS     5
  43  struct qcom_pcie_resources_2_1_0 {
  44 @@ -184,6 +187,7 @@ struct qcom_pcie {
  45         struct phy *phy;
  46         struct gpio_desc *reset;
  47         const struct qcom_pcie_ops *ops;
  48 +       int gen;
  49  };
  50
  51  #define to_qcom_pcie(x)                dev_get_drvdata((x)->dev)
  52 @@ -397,6 +401,11 @@ static int qcom_pcie_init_2_1_0(struct q
  53         /* wait for clock acquisition */
  54         usleep_range(1000, 1500);
  55
  56 +       if (pcie->gen == 1) {
  57 +               val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
  58 +               val |= PCI_EXP_LNKSTA_CLS_2_5GB;
  59 +               writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
  60 +       }
  61
  62         /* Set the Max TLP size to 2K, instead of using default of 4K */
  63         writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
  64 @@ -1261,6 +1270,10 @@ static int qcom_pcie_probe(struct platfo
  65                 goto err_pm_runtime_put;
  66         }
  67
  68 +       pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
  69 +       if (pcie->gen < 0)
  70 +               pcie->gen = 2;
  71 +
  72         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
  73         pcie->parf = devm_ioremap_resource(dev, res);
  74         if (IS_ERR(pcie->parf)) {