git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 16 Dec 2023 12:07:23 +0800
   4 Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength
   5  for orangepi r1 plus lts
   6
   7 The default strength is not enough to provide stable connection
   8 under 3.3v LDO voltage.
   9
  10 Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
  11 Cc: stable@vger.kernel.org # 6.6+
  12 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  13 Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
  14 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  15 ---
  16  arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++-
  17  1 file changed, 3 insertions(+), 1 deletion(-)
  18
  19 --- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
  20 +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
  21 @@ -26,9 +26,11 @@
  22                         compatible = "ethernet-phy-ieee802.3-c22";
  23                         reg = <0>;
  24
  25 +                       motorcomm,auto-sleep-disabled;
  26                         motorcomm,clk-out-frequency-hz = <125000000>;
  27                         motorcomm,keep-pll-enabled;
  28 -                       motorcomm,auto-sleep-disabled;
  29 +                       motorcomm,rx-clk-drv-microamp = <5020>;
  30 +                       motorcomm,rx-data-drv-microamp = <5020>;
  31
  32                         pinctrl-0 = <&eth_phy_reset_pin>;
  33                         pinctrl-names = "default";