projects / openwrt / staging / stintel.git / blob
? search:


01eed6cc01be4495033bb8c3f25c4a5c2c3f1bff
[openwrt/staging/stintel.git] /
1 From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
3 Date: Fri, 20 Jan 2023 10:20:35 +0100
4 Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
5 composites
6
7 Like done for cpumux clocks, propagate struct device for composite
8 clocks registered through clk-mtk helpers to be able to get runtime
9 pm support for MTK clocks.
10
11 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
12 Tested-by: Miles Chen <miles.chen@mediatek.com>
13 Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
14 Tested-by: Mingming Su <mingming.su@mediatek.com>
15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
16
17 [daniel@makrotopia.org: remove parts not relevant for OpenWrt]
18 ---
19 drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
20 drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
21 drivers/clk/mediatek/clk-mt7622.c | 8 +++++---
22 drivers/clk/mediatek/clk-mt7629.c | 8 +++++---
23 drivers/clk/mediatek/clk-mtk.c | 11 ++++++-----
24 drivers/clk/mediatek/clk-mtk.h | 3 ++-
25 6 files changed, 32 insertions(+), 20 deletions(-)
26
27 --- a/drivers/clk/mediatek/clk-mt2701.c
28 +++ b/drivers/clk/mediatek/clk-mt2701.c
29 @@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat
30 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
31 clk_data);
32
33 - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
34 - base, &mt2701_clk_lock, clk_data);
35 + mtk_clk_register_composites(&pdev->dev, top_muxes,
36 + ARRAY_SIZE(top_muxes), base,
37 + &mt2701_clk_lock, clk_data);
38
39 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
40 base, &mt2701_clk_lock, clk_data);
41 @@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf
42 mtk_clk_register_gates(&pdev->dev, node, peri_clks,
43 ARRAY_SIZE(peri_clks), clk_data);
44
45 - mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
46 - &mt2701_clk_lock, clk_data);
47 + mtk_clk_register_composites(&pdev->dev, peri_muxs,
48 + ARRAY_SIZE(peri_muxs), base,
49 + &mt2701_clk_lock, clk_data);
50
51 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
52 if (r)
53 --- a/drivers/clk/mediatek/clk-mt2712.c
54 +++ b/drivers/clk/mediatek/clk-mt2712.c
55 @@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
56 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
57 top_clk_data);
58 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
59 - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
60 - &mt2712_clk_lock, top_clk_data);
61 + mtk_clk_register_composites(&pdev->dev, top_muxes,
62 + ARRAY_SIZE(top_muxes), base,
63 + &mt2712_clk_lock, top_clk_data);
64 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
65 &mt2712_clk_lock, top_clk_data);
66 mtk_clk_register_gates(&pdev->dev, node, top_clks,
67 @@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
68
69 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
70
71 - mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
72 - &mt2712_clk_lock, clk_data);
73 + r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
74 + ARRAY_SIZE(mcu_muxes), base,
75 + &mt2712_clk_lock, clk_data);
76 + if (r)
77 + dev_err(&pdev->dev, "Could not register composites: %d\n", r);
78
79 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
80
81 --- a/drivers/clk/mediatek/clk-mt7622.c
82 +++ b/drivers/clk/mediatek/clk-mt7622.c
83 @@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
84 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
85 clk_data);
86
87 - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
88 - base, &mt7622_clk_lock, clk_data);
89 + mtk_clk_register_composites(&pdev->dev, top_muxes,
90 + ARRAY_SIZE(top_muxes), base,
91 + &mt7622_clk_lock, clk_data);
92
93 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
94 base, &mt7622_clk_lock, clk_data);
95 @@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
96 mtk_clk_register_gates(&pdev->dev, node, peri_clks,
97 ARRAY_SIZE(peri_clks), clk_data);
98
99 - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
100 + mtk_clk_register_composites(&pdev->dev, peri_muxes,
101 + ARRAY_SIZE(peri_muxes), base,
102 &mt7622_clk_lock, clk_data);
103
104 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
105 --- a/drivers/clk/mediatek/clk-mt7629.c
106 +++ b/drivers/clk/mediatek/clk-mt7629.c
107 @@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat
108 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
109 clk_data);
110
111 - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
112 - base, &mt7629_clk_lock, clk_data);
113 + mtk_clk_register_composites(&pdev->dev, top_muxes,
114 + ARRAY_SIZE(top_muxes), base,
115 + &mt7629_clk_lock, clk_data);
116
117 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
118 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
119 @@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf
120 mtk_clk_register_gates(&pdev->dev, node, peri_clks,
121 ARRAY_SIZE(peri_clks), clk_data);
122
123 - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
124 + mtk_clk_register_composites(&pdev->dev, peri_muxes,
125 + ARRAY_SIZE(peri_muxes), base,
126 &mt7629_clk_lock, clk_data);
127
128 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
129 --- a/drivers/clk/mediatek/clk-mtk.c
130 +++ b/drivers/clk/mediatek/clk-mtk.c
131 @@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
132 }
133 EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
134
135 -static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
136 - void __iomem *base, spinlock_t *lock)
137 +static struct clk_hw *mtk_clk_register_composite(struct device *dev,
138 + const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
139 {
140 struct clk_hw *hw;
141 struct clk_mux *mux = NULL;
142 @@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
143 div_ops = &clk_divider_ops;
144 }
145
146 - hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
147 + hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
148 mux_hw, mux_ops,
149 div_hw, div_ops,
150 gate_hw, gate_ops,
151 @@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
152 kfree(mux);
153 }
154
155 -int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
156 +int mtk_clk_register_composites(struct device *dev,
157 + const struct mtk_composite *mcs, int num,
158 void __iomem *base, spinlock_t *lock,
159 struct clk_hw_onecell_data *clk_data)
160 {
161 @@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
162 continue;
163 }
164
165 - hw = mtk_clk_register_composite(mc, base, lock);
166 + hw = mtk_clk_register_composite(dev, mc, base, lock);
167
168 if (IS_ERR(hw)) {
169 pr_err("Failed to register clk %s: %pe\n", mc->name,
170 --- a/drivers/clk/mediatek/clk-mtk.h
171 +++ b/drivers/clk/mediatek/clk-mtk.h
172 @@ -149,7 +149,8 @@ struct mtk_composite {
173 .flags = 0, \
174 }
175
176 -int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
177 +int mtk_clk_register_composites(struct device *dev,
178 + const struct mtk_composite *mcs, int num,
179 void __iomem *base, spinlock_t *lock,
180 struct clk_hw_onecell_data *clk_data);
181 void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
Staging tree of Stijn Tintel