git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From d5f901eab2e9dfed1095995dfc98f231f4fd2971 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Wed, 27 Jul 2022 13:35:13 +0200
   4 Subject: [PATCH 04/14] net: dsa: qca8k: move qca8k read/write/rmw and reg
   5  table to common code
   6
   7 The same reg table and read/write/rmw function are used by drivers
   8 based on qca8k family switch.
   9 Move them to common code to make it accessible also by other drivers.
  10
  11 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  12 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  14 ---
  15  drivers/net/dsa/qca/qca8k-8xxx.c   | 42 ------------------------------
  16  drivers/net/dsa/qca/qca8k-common.c | 38 +++++++++++++++++++++++++++
  17  drivers/net/dsa/qca/qca8k.h        |  6 +++++
  18  3 files changed, 44 insertions(+), 42 deletions(-)
  19
  20 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
  21 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
  22 @@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv,
  23         return 0;
  24  }
  25
  26 -static int
  27 -qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
  28 -{
  29 -       return regmap_read(priv->regmap, reg, val);
  30 -}
  31 -
  32 -static int
  33 -qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
  34 -{
  35 -       return regmap_write(priv->regmap, reg, val);
  36 -}
  37 -
  38 -static int
  39 -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
  40 -{
  41 -       return regmap_update_bits(priv->regmap, reg, mask, write_val);
  42 -}
  43 -
  44  static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
  45  {
  46         struct qca8k_mgmt_eth_data *mgmt_eth_data;
  47 @@ -483,30 +465,6 @@ exit:
  48         return ret;
  49  }
  50
  51 -static const struct regmap_range qca8k_readable_ranges[] = {
  52 -       regmap_reg_range(0x0000, 0x00e4), /* Global control */
  53 -       regmap_reg_range(0x0100, 0x0168), /* EEE control */
  54 -       regmap_reg_range(0x0200, 0x0270), /* Parser control */
  55 -       regmap_reg_range(0x0400, 0x0454), /* ACL */
  56 -       regmap_reg_range(0x0600, 0x0718), /* Lookup */
  57 -       regmap_reg_range(0x0800, 0x0b70), /* QM */
  58 -       regmap_reg_range(0x0c00, 0x0c80), /* PKT */
  59 -       regmap_reg_range(0x0e00, 0x0e98), /* L3 */
  60 -       regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
  61 -       regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
  62 -       regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
  63 -       regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
  64 -       regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
  65 -       regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
  66 -       regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
  67 -
  68 -};
  69 -
  70 -static const struct regmap_access_table qca8k_readable_table = {
  71 -       .yes_ranges = qca8k_readable_ranges,
  72 -       .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
  73 -};
  74 -
  75  static struct regmap_config qca8k_regmap_config = {
  76         .reg_bits = 16,
  77         .val_bits = 32,
  78 --- a/drivers/net/dsa/qca/qca8k-common.c
  79 +++ b/drivers/net/dsa/qca/qca8k-common.c
  80 @@ -61,3 +61,41 @@ const struct qca8k_mib_desc ar8327_mib[]
  81         MIB_DESC(1, 0xa8, "RXUnicast"),
  82         MIB_DESC(1, 0xac, "TXUnicast"),
  83  };
  84 +
  85 +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
  86 +{
  87 +       return regmap_read(priv->regmap, reg, val);
  88 +}
  89 +
  90 +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
  91 +{
  92 +       return regmap_write(priv->regmap, reg, val);
  93 +}
  94 +
  95 +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
  96 +{
  97 +       return regmap_update_bits(priv->regmap, reg, mask, write_val);
  98 +}
  99 +
 100 +static const struct regmap_range qca8k_readable_ranges[] = {
 101 +       regmap_reg_range(0x0000, 0x00e4), /* Global control */
 102 +       regmap_reg_range(0x0100, 0x0168), /* EEE control */
 103 +       regmap_reg_range(0x0200, 0x0270), /* Parser control */
 104 +       regmap_reg_range(0x0400, 0x0454), /* ACL */
 105 +       regmap_reg_range(0x0600, 0x0718), /* Lookup */
 106 +       regmap_reg_range(0x0800, 0x0b70), /* QM */
 107 +       regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 108 +       regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 109 +       regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 110 +       regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 111 +       regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 112 +       regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 113 +       regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 114 +       regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 115 +       regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 116 +};
 117 +
 118 +const struct regmap_access_table qca8k_readable_table = {
 119 +       .yes_ranges = qca8k_readable_ranges,
 120 +       .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 121 +};
 122 --- a/drivers/net/dsa/qca/qca8k.h
 123 +++ b/drivers/net/dsa/qca/qca8k.h
 124 @@ -416,5 +416,11 @@ struct qca8k_fdb {
 125
 126  /* Common setup function */
 127  extern const struct qca8k_mib_desc ar8327_mib[];
 128 +extern const struct regmap_access_table qca8k_readable_table;
 129 +
 130 +/* Common read/write/rmw function */
 131 +int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
 132 +int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
 133 +int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
 134
 135  #endif /* __QCA8K_H */